index - Equipe Secure and Safe Hardware

 

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Reliability Side-Channel Analysis SCA Fault injection attack Field Programmable Gates Array FPGA Robustness Countermeasures Switches Spin transfer torque Machine learning Lightweight cryptography Dual-rail with Precharge Logic DPL Training Security MRAM Randomness Image processing Gem5 FPGA Countermeasure SCA Intrusion detection Signal processing algorithms Protocols Hardware security Costs Fault attacks PUF Aging 3G mobile communication Defect modeling Temperature sensors TRNG Dynamic range Fault injection Estimation Masking Random access memory Electromagnetic Power demand EMFI RSA Magnetic tunnel junction Side-Channel Attacks STT-MRAM GSM Memory Controller Linearity Side-channel attack CRT ASIC OCaml Convolution Mutual Information Analysis MIA Sensors Loop PUF Formal methods Formal proof Application-specific VLSI designs Resistance Reverse engineering Elliptic curve cryptography FDSOI Asynchronous Reverse-engineering Side-Channel Analysis Authentication AES Masking countermeasure Side-channel attacks Coq Confusion coefficient Voltage Differential Power Analysis DPA Neural networks Magnetic tunneling Internet of Things Circuit faults Information leakage Side-channel analysis Routing Computational modeling CPA Transistors Simulation SoC Receivers Security and privacy Differential power analysis DPA Filtering Field programmable gate arrays Security services Cryptography Process variation Writing Energy consumption Hardware Power-constant logic Logic gates DRAM Side-channel attacks SCA

 

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