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DERNIERS DÉPÔTS - LATEST DOCUMENTS
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Diamante-Simone Crescenzo, Rafael Carrera Rodriguez, Riccardo Alidori, Florent Bruguier, Emanuele Valea, et al.. Hardware accelerator for FIPS 202 hash functions in post-quantum ready SoCs. IOLTS 2024 - IEEE 30th International Symposium on On-Line Testing and Robust System Design, Jul 2024, Rennes, France. ⟨10.1109/IOLTS60994.2024.10616067⟩. ⟨cea-04689662⟩
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Valentin Isaac Chassande, Adrian Evans, Yves Durand, Frédéric Rousseau. SpDCache: Region-Based Reduction Cache for Outer-Product Sparse Matrix Kernels. 35th IEEE International Conference on Application-specific Systems, Architectures and Processors, Jul 2024, Hong-Kong, Hong Kong SAR China. ⟨10.1109/ASAP61560.2024.00012⟩. ⟨cea-04676685⟩
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Léo de la Fuente, Jean-Frédéric Christmann, Manuel Pezzin, Matthias Remars, Olivier Sentieys. A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories. ISCAS 2024 - IEEE International Symposium on Circuits and Systems, May 2024, Singapour, Singapore. ⟨10.1109/ISCAS58744.2024.10557870⟩. ⟨cea-04676665⟩
Pour toute question : hal@cea.fr
Nombre de textes intégraux
356
Nombre de notices sans document
316
Indicateur d'Open Access
59 %
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RRAM
Network-on-chip
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Heterogeneous computing
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Continual learning
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Hardware
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